The present invention relates to a hierarchical memory system, for instance, a memory system comprising a buffer memory and a main memory, and more particularly to the control of a memory system of the type in which the storing of updated data into an upper level memory is carried out according to the swap or store-in system.
In a hierarchical memory system in which a lower level memory (e.g. buffer memory) contains a partial copy of the content of an upper level memory (e.g. main memory), according to the wellknown swap or store-in system, when a processor updates certain data in the lower level memory, the corresponding data in the upper level memory is not updated, but, when a block containing this updated data is replaced with another block from the upper level memory, the replaced block is transferred to the upper level memory and stored therein, thereby to update the content of the upper level memory. The data transfer from the lower level memory to the upper level memory for such purpose is hereinafter referred to as swap-out. An improvement of this system is described in the Japanese Patent Publication No. 16262/1983. In this improvement, a memory (hereinafter referred to as a swap-out buffer) for temporarily storing the data of a block to be swapped out (hereinafter referred to as swap-out data) is provided. On the occasion of swapping-out, swap-out data from the lower level memory is moved into the swap-out buffer while a transfer request for the desired block is issued to the upper level memory, and, after the transfer from the upper level memory to the lower level memory is completed, the swap-out data in the swap-out buffer is transferred to the upper level memory. This process will later be described in more detail. By this improvement, it is not necessary to complete the transfer of swap-out data to the upper level memory before transferring a new data block to the lower level memory, and, accordingly, the time required before obtaining the desired data is shortened.
On the other hand, as an improvement for increasing the capacity of the lower level memory, a system in which a plurality of data blocks are contained in one entry (access unit specified by a row address and column address) of the lower level memory (later described in detail) is described in the Japanese Patent Publication No. 12222/1982. This system is advantageous in the point that it is of low cost as compared with a solution by increasing the number of columns.
However, if the above-mentioned swap-out buffer system is directly applied to this multiple-block-per-entry system, the data transfer from the upper level memory is not executed till the data of all blocks requiring swap-out in one entry is moved into the swap-out buffer, and, as a result, if there are many blocks to be swapped out, the data transfer from the upper level memory will be delayed. In addition, the swap-out buffer must have a capacity which can contain all the blocks in one entry.